AN EFFICIENT METHOD FOR STANDBY POWER REDUCTION IN LOW POWER CMOS CIRCUITS

Abstract

Reduction in leakage has becomes an important concern in low-voltage, low power and high-performance VLSI applications. There, is a growing need for low-voltage, high performance and low power system, especially for portable and battery powered applications. Since these applications often remains in stand-by mode significantly longer than in active mode, their stand-by (or leakage) current has a dominant impact on the battery life. As technology scales down, leakage has become a very important issue for the VLSI professionals; therefore new methods for leakage reduction are critically needed. It has becoming a common approach in low power design is to target the designs, where parts of the circuit are put in "standby mode" which is not in use. Also the leakage current/power is a state dependent which can be exploited to produce standby/leakage power saving. Keeping these in mind, a new method for standby power reduction is presented, that can be used during the logic design of the CMOS circuits. The problem is to determine the minimum leakage vector (MLV), on which the circuit can be forced in the standby mode. For this, the significant transistor groups, which need to be of high-Vt, are proposed for each logic gate corresponding to each input state. These groups are obtained based on the observations that a single transistor is sufficient to produce significant reduction in leakage current/power. Now depending upon the input state, these groups are applied to complex circuits. These circuits have two to thirty-two inputs. For circuits having 2 to 8 inputs, all input states are tried and there corresponding results are obtained. From the observation of these circuits, only selective input states are tried in 10, 16 and 32-inputs circuits because of a large number of input states. To determine MLV, the standby power, delay and total (dynamic) power all are taken into account. A delay limit of 25% increase is fixed for MLV determination. Considering all the input states, a state is chosen which presents significant reduction in standby as well as total power, without exceeding the fixed delay limit. The results obtained in show that the standby power reduction is in the range of 98%-99%, decrease in total power dissipation is ranges from3l.05% to as high as 75.16% with increase in delay of 7.59%-22.30% at MLV for every circuit. There is no area over head involved. No technology modification is requiring in this methods. This can be implemented in already existing dual-Vt process All the simulation results are obtained using T-spice having BSIM3.2 model for a 0.5um MOSIS process technology. The circuits are simulated at 1-V supply voltage while low and high threshold voltages are chosen as 0.2V and 0.4V respectively.