Abstract:
Device scaling in deep Submicron technology shrinkage the spacing between adjacent interconnect, which leads to increase coupling effect between wires. Continuous device scaling much improved the gates delay. However, interconnect delays have not scaled in that proportion Therefore a need for accurate and computationally effective models in the early stages of the chip design process to assess or optimize issues affecting these interconnects becomes necessary.
This thesis presents the description of a finite difference time domain (FDTD) method that is intended for estimation of voltages and currents on transmission line. Interconnect performance such as crosstalk, delay, crosstalk induce delay are analyzed using FDTD technique. For motivation, analytical results based on proposed model is also compared with HSPICE simulated result. Analytical results are observed in closed agreement with HSPICE results, which proves the validity of proposed model.
