Abstract:
It was observed for so many years that most of the time only simple instructions are used and even complex instructions can be replaced with simple instructions written together. Since computer based on RISC architecture use very simple instructions. So it is topic of very interest. RISC architecture use internal registers most of the tune. They use hardwired approach which further simplifies the design of processor. External memory is accessed by only LOAD and STORE instructions.
RISC performance is increased over CISC architecture because of pipelining. Pipelining is a concept of dividing the task of instruction execution into pieces. It is just like a inline system used in industries to enhance the profit. Each piece is given to an individual phase.The responsibility of each phase is fixed. Since single instruction takes same time for execution as in sequential execution, parallel operations on instructions in different stages reduces the overall time of execution. The balance of work between different stages of pipelining is important as the slowest stage of the pipeline decides the throughput of the processor. The consequences of pipelining are the structural hazards, data hazards and control hazards. They can be handled using the methods of forwarding, stalling and flushing. Stalling degrades the performance by delaying the instruction execution. Prefetching unit is designed which works as a small cache. It is used to prefetch the instructions from memory and stored them inside the buffer.
The processor presented in this thesis can handle handles the hardware interrupts and exceptions. RESET has the highest priority. Six external hardware interrupts are available and are vectored. It is also capable to handle overflow and undefined instructions.
This microprocessor is designed with help of VHDL as synthesis tool. . Hierarchical approach is used for modeling the RISC processor. Basics units are described using behavioral programming and they are interconnected using structural programming to form complete RISC processor.
