Abstract:
Principle of gate controller is based on Moore finite state machine. Moore finite state machine output depends on the current state. Basically gate controller is an up-down counter, which count the vehicles with particular conditions.
In the first stage, the state diagram is drawn then it was coded in VHDL and these codes were simulated on ModelSim. ModelSim is simulator package for VHDL and Verilog-HDL. For obtaining gate level circuit of these codes, these c-odes were synthesized on Synopsys Tool using Isi_l0k library for optimization. Schematic simulation of obtained circuit was also performed in Xilinx Foundation 2.1. The Layout of cells was checked using Design Rule Checker.
Finally, the Spice file of Layout is extracted by spice file compiler. This spice file used for simulating the performance of chip. Layout performance is than verified by simulating this spice file.
