Abstract:
Fast Fourier Transform is considered as one of the most powerful tools in digital signal processing with its wide applications in speech processing, image processing and communication systems. Pipelined FFT processors are one specific set of FFT processors which strike a reasonable balance between the data throughput and hardware complexity. Out of all the pipelined architectures, Radix-22 single path delay feedback (SDF) architecture has minimum hardware cost and maximum resource utilization. Hence, it is taken as the base architecture for our FFT processor. Moreover, as various communication standards and protocols require FFT’s of variable sizes, our thesis aims at developing a reconfigurable Radix-22 SDF processor that can accommodate three different FFT sizes. Three different reconfigurable architectures have been implemented which suit various requirements. In one of the architectures, Multi-streaming has also been considered to account for high throughput rate. Further, the ROM’s to store Twiddle factors have been replaced by twiddle factor generators which follow COrdinate Rotation DIgital Computer (CORDIC) algorithm. All the data handling is done using IEEE-754 32-bit single precision floating point operations. These architectures coded in Verilog HDL, synthesized in Xilinx ISE 14.5 and mapped onto xc7vx485t-2ffg1761 FPGA device from Virtex-7 VC707 evaluation board. Their performance in terms of hardware cost, maximum operating frequency, latency and throughput in computation of FFT has been summarized and the performance of the three different reconfigurable architectures has been compared
