DESIGN AND VERIFICATION OF THREE PHASE SEQUENCE DETECTOR

Abstract

The work proposes a three-phase sequence detector which will be capable of extracting the three phase sequences of a balanced or unbalanced power system which can be the result of any faults in the phases and or ground, unbalanced loading and open phases. The extraced sequences are the positive, negative and zero sequences components. Digital simulation is used here to process the three-phase input signal which can be balanced or unbalanced. To process the three-phase signal, the conventional symmetrical component transform method in implemented here. Finally, a Field Programmable Gate Array (FPGA) implementation is used here to verify the theoritical results.