Abstract:
Rapid development in the technology of memories has grown the interest in spintronic field in the last few years. The main reason of this is Moore’s law reaching towards its physical limit below 45nm. The static power dissipation in complementary metal oxide semiconductor (CMOS) technology become a bottleneck for further scaling. The spintronics is the best substitute to replace the CMOS technology in future because of its property of zero stand by power and non-volatility. The magnetic tunnel junction (MTJ) is the fundamental device to store the logics. The MTJs have two types (i) in-plane MTJ (IMTJ) (ii) perpendicular MTJ (PMTJ). The PMTJ is more efficient than IMTJ because it requires less write current and high scalability. Spintronics based memories such as spin transfer torque magnetic random access memory (STT-MRAM) uses spin property of an electron to differentiate between logic ‘0’ and logic ‘1’. In the last few decades, the leading memories are dynamic random access memory (DRAM), static random access memory (SRAM) and flash memory. These memories have some drawbacks such as SRAM has high standby leakage power, large on chip area. DRAM manufacturing process is complex and it is required refreshing current periodically. Flash memory (non-volatile) requires excess write power. There is a requirement for single memory that can overcome the limitation of the existing memory technologies. The aim of this dissertation is to explain performance analysis of non-volatile memories based logic gates at the depth. I mainly focused on spin valve, magnetic tunnel junction (MTJ), STT-MRAM, read/write operation, and spin orbit torque (SOT), read/write operation of SOT, differential spin Hall effect (DSH) based MRAM, read write operation of DSH-MRAM, logic gates based on STT/DSH-MRAM and the analysis of the STT and DSH switching techniques. Spintronics based memories are the capable candidate for the future universal memories has properties such as low power consumption, small access time, high endurance, high density, low cost per bit, non-volatility and small on chip area.
