Abstract:
thermionic injection of electrons over the barrier in the metal-oxide-semiconductor Field Effect Transistors imposes a fundamental limitation to the steep transition. Thus electro-statically, a new device to provide steep slope and high drive current is the need of the time in order to improve the energy efficiency of the circuits [1], [2]. Over the last decade, the journey of Tunneling FETs (TFETs) for improving the drive capability and the subthreshold slope (SS) has directed to the proposal of many new device architecture. An optimization of device architecture and source/channel/drain material and doping is being strongly pursued [3]. The two main tunneling mechanism are as follows: one is lateral (point) tunneling, whereby the tunneling takes place between in parallel to the gate. Other one is line (vertical) tunneling, whereby the tunneling is perpendicular to the gate [4]. In later case the area of cross section for tunneling is increased which improves the drive current and SS. The analog and digital application of TFETs are extensively being explored due to its unique saturation characteristics [5], [6]. Recently, tunnel FETs for internet-of-things applications have been successfully demonstrated experimentally [7]. The focus of research on TFETs is mostly concentrated on the drive currents and steep slopes. The role of interface traps and quantum confinements have also been well addressed [8], [9].
The main concern of TFET based analog circuits is to identify the drain current saturation voltage (VDSAT) of the device to bias the circuits properly. The architecture of the point and line tunneling devices are different in nature and hence the associated physics behind the drain current saturation is also different. The saturation in both the point and line TFETs occur at a constant difference between the gate and drain bias. Till now, the estimation of VDSAT for TFETs are being made as the voltage required to reach 90-95% of the maximum drain current [10], [11]. These methods are merely rough estimation of VDSAT and are not physics based. The correct estimation of VDSAT also provides the trends of analog performance parameters in saturation regimes. A few researchers have discussed the saturation in point TFETs but the saturation of drain current in line TFETs have not been addressed. Moreover, the device design parameters strongly affects the saturation characteristics, especially the value of VDSAT. So there is a need of device/circuit design guidelines using TFETs. The influence of saturation voltages on the analog circuit performance is also yet to be discussed analytically.
