Abstract:
The proposed phase locking scheme is based on the principle of adaptive sampling period aclJusl.mclit.. It variably changes its sampiing period to generate the output signal in synchronism with the incoming input signal in terms of phase and frequency. The phase error between input signal and the look up table generated signal is calculated by a mull. iplier. The phase locked 1001) acts to minimize this phase error by generating sampling pulses which are having variable pulse width. 'l'lie purpose of PLL is very basic and its application area varies from power system to (ouhirmunicat ion system. 'l'his report. covers grid synchronization and FM demodulation as two 111W 1 applications. The scheme can be used on any frequency range and it. is tested on 50 Hz and 10 kllz. The proposed scheme is also tested in various fault. sit uation. The important parameters like lock-in range, pull-in range, and hold-in range are calculated for proposed scheme. The simulation results shows that the proposed sclmeimie has wide lock-in range and it exhibits quick acquisition of input signal. The simulation and hardware implemnentatiomi of the proposed scheme are (lone on FPGA. The ohectives of this work include: Study of different types of phase locked loops. To propose a novel phase locked 1oop. Simulate the adaptive sampling period based PLL under different conditions. Implement the proposed scheme on FPGA. To apply the scheme in FM demodulation and grid synchronization.
