Abstract:
To achieve higher packing density and improved performance, CMOS devices have
been continuously scaled down from last few decades. The reduction in feature size makes
power consumption to be a critical issue in nanoscale CMOS VLSI circuits. In order to
maintain the power consumption under control, supply voltage (Vdd) and threshold voltage
(V,j,) has to be commensurately scaled to achieve an improved performance. However, the
reduction in V/h results in substantial increment in leakage currents which degrades device
performance in nanoscale regime.
Input vector control (lVC) is a popular technique for leakage power reduction. It
utilizes the transistor stack effect in CMOS gates by applying a minimum leakage vector
(MLV) to the primary inputs of combinational circuits during the standby mode. CMOS
gate's sub threshold leakage current varies dramatically with the input vector applied to the
gate, the idea of IVC technique is to manipulate the input vector with the help of a sleep
signal to reduce the leakage when the circuit is at the standby mode. However, this technique
becomes less effective for technology nodes below 32nm. Various circuit level techniques for
leakage reduction includes reverse body biasing, gate oxide variation, pin reordering and logic
reconstruction. Applying dual T0 along with stacking in non critical paths can reduce leakage
to a greater extent not only in standby mode but also in active mode. We can apply pin
reordering technique which is a post processing step that has a low layout impact and is
therefore an inexpensive optimization for leakage and delay.
Besides this technique, the reverse body bias variation technique along with stacking
helps in reduction of subthreshold leakage to a greater extend. With the variation in reverse
body bias voltage, transistor threshold voltage (V,,,) can be increased which substantially
reduces subthreshold leakage current. On the other hand, gate oxide thickness (T0 ) can be
increased to modify threshold voltage and reduce subthreshold and gate tunneling leakage in a
CMOS VLSI circuit. These approaches should be carefully used as the increase in T0 and V:h,
the device suffers from adverse short channel effects. Along with these techniques, pin
reordering and logic reconstruction can be used which are low cost and powerful techniques
for leakage and delay reduction.
