POWER QUALITY IMPROVEMENT USING MODULAR D-STATCOM

Abstract

In present scenario, majority of loads such as motor drives, fans, pumps, and power electronic converters put reactive power burden on the distribution systems. Excessive reactive power demand results into low power factor, poor voltage regulation and increases feeder losses and reduces the active power flow capability of the distribution system. Moreover, situation worsens in the presence of non-linear loads and raises power quality issues on distribution system. The primary source that draw non-linear currents from the distribution systems are power electronic devices. The operation of non-linear loads on distribution systems draw harmonics currents, which may interrupt the normal operation of other electrical equipment connected to the network. With ever-increasing penetration of power electronic devices, the power quality problem is becoming more challenging. At the same time these equipments are typically equipped with sophisticated microprocessor-based controllers which are quite sensitive to deviations of the voltage from its ideal waveform. In recent years, with the advent of sophisticated electrical and electronic equipment, the electric power quality (PQ) has become an issue of concern and extensive research is being carried out to improve the power quality. In the early days, synchronous condenser and mechanically switched capacitors and inductors have been used for reactive power compensation. However, due to their slow response and mechanical wear and tear, use of these devices is limited for the applications where fast compensation is not needed. With the advent of the first generation of Flexible AC Transmission System (FACTS) devices, thyristor-controlled static var compensators (SVCs) schemes made significant advances in reactive power compensation as these devices are fast in operation and smooth control of reactive power compensation can be obtained with these devices. Despite the attractive theoretical simplicity of the SVC schemes, their penetration has been hindered by a number of disadvantages such as large size of capacitor and inductor banks, dependency of the reactive power compensation on operating voltage. With the remarkable progress of gate commutated semiconductor devices, attention has been focused on second generation FACTS devices which are based on self-commutated inverters. Among them, Static Synchronous Compensator (STATCOM) has attracted more attention of researches and power industry for reactive power compensation and voltage regulation in transmission systems. Harmonic regulations or guidelines such as IEEE 519-1992 and IEC 61000 have become acceptable standards and are being applied to limit the current and voltage harmonics levels. To ii meet these requirements, harmonics must be mitigated by using harmonic filters. Active and passive filters are used either together to form hybrid filters or separately to mitigate harmonics. Conventional power quality mitigation equipment can respond only to a particular power quality problem, and this fact has attracted the attention of power engineers to develop dynamic and adjustable solutions to power quality problems. One modern and very promising group of solutions that deals with load current and/or supply voltage imperfections is the Custom Power Devices (CPDs). CPDs rectify most of the distribution system problems and many of the existing compensation devices are being replaced by CPDs, thereby reducing the cost. The family of CPDs includes distribution static synchronous compensator (D-STATCOM), dynamic voltage restorer (DVR) and unified power quality conditioners (UPQC) which are used for compensating the power quality problems in the current and/or voltage waveforms. Among these members, DSTATCOM is a shunt-connected device, which takes care of the power quality problems in the current waveform. In this thesis, an attempt has been made to develop a robust computercontrolled D-STATCOM for power quality improvement in single phase and 3P3W distribution systems. It is well known that high performance and cost-effective inverter is a prerequisite for the realization of a D-STATCOM. These inverters can be broadly categorised into two classes, namely, voltage source inverter (VSI) and current source inverter (CSI). A critical comparison of the performance of VSI and CSI when used as a power circuit of D-STATCOM is beyond the scope of this thesis. However, in the present work, VSI has been considered as a power circuit for D-STATCOM as it has higher market penetration and a more noticeable development on VSI has taken place over the last decade, in comparison to CSI topologies. The high harmonic content of the output voltage makes basic six-pulse (two-level) VSI impractical for direct use in high-power, medium-voltage applications. Instead of using filters and connecting several switching devices in series to achieve the required voltage level, several alternative possible solutions are reported in the literature and can be broadly categorized into two groups: multipulse and multilevel inverters. The first one requires complex phase-shifting transformers and therefore, its application is limited to high-power, high-voltage systems. The second approach, multilevel inverters, uses the concept of addition of multiple small voltage levels for achieving the required voltage level with the help of additional switching devices and few components like diodes or capacitors. This approach does not require complex phase shifting transformers and hence these topologies are best suited for medium-power applications. The common multilevel inverters (MLI) topologies are the diode-clamped (DCMLI), flying capacitor (FCMLI), and cascaded multilevel inverters (CMLI) or modular multilevel cascade inverters (MMCI). iii The selection of individual inverter topologies for D-STATCOM applications depends on their performance, cost, size, and implementation issues. DCMLI topology seems to be the most suited for D-STATCOM applications. But, the large number of power components and voltage unbalance problem at higher levels limits the DCMLI for low power rating applications. On the other hand, FCMLI has a natural voltage balancing operation and modular structure, but its application as a D-STATCOM is limited due to the requirement of large number of capacitors and their pre-charging. On the other hand, MMCI is one of the next generation multilevel inverters intended for high or medium-voltage power conversion without the requirement of line-frequency transformers. The MMCI is based on cascade connection of multiple single-phase H-bridge converter cells per leg. Among the members of MMCI, single-star bridge cell (SSBC) and single-delta bridge cell (SDBC) are characterized by the cascade connection of multiple single-phase H-bridge cells per leg. The least component requirement, low cost, modular structure, easy expansion to any number of levels, high fault tolerance and absence of complex input transformer and non-initialization of the capacitor voltages make SSBC and SDBC best suited for D-STATCOM applications. Both SSBC and SDBC can reach higher output voltages and power levels (13.8 kV, 30 MVA) with readily available medium-voltage semiconductor devices. The SSBC and SDBC inverters have found input transformerless applications such as STATCOM, Battery Energy Storage System (BESS), and DVR. In this work, the application of MMCI has been extended to D-STATCOM, intended for direct installation on a medium-voltage distribution system for reactive power compensation and harmonic compensation. Towards this goal, the SSBC based inverter configuration has been chosen over SDBC as the number of converter-cells required for SDBC is 1.732 (= 3 ) times that required for SSBC. In order to control the output voltage of the inverter of D-STATCOM to act as a controllable current source, a suitable modulation technique is be required for the SSBC inverter. Although a large number of different modulation schemes for multilevel inverters have been proposed in the literature, for industrial application, carrier based PWM schemes are still preferred because of their proven technology, simplicity and ease of implementation. The carrier-based modulation schemes for multilevel inverters can be generally classified into two categories: phase-shifted PWM (PSPWM) and level-shifted PWM (LSPWM) techniques. The LSPWM technique produces the better harmonic performance when compared with the PSPWM technique, but it avoids the current harmonic cancellation at the input side of the phaseshifting transformer. Nevertheless, because of the unequal device conduction periods of the iv LSPWM technique, it has penetrated smaller market even in those applications where transformer is not required at the input side, such as FACTS and CPDs, electric vehicle applications. The unequal device conduction periods affect the charging and discharging of the dc bus capacitors and cause non-uniform power and heat distribution in the inverter. The PSPWM distribute the switching and conduction losses evenly if the H-bridges characteristics are ideal. However if the devices characteristics are uneven or the SSBC inverter is supplying the unbalanced currents in PSPWM, the capacitor voltages deviate from the reference voltage. To prove this statement, a five level inverter the losses in a H-bridge are modeled in MATLAB from the data sheet of device characteristics to observe uneven losses among the H-bridges when supplying the unbalanced current or with different devices. In the present work, the control algorithms for capacitor voltage balancing are extended to single phase and three phase SSBC inverter with PSPWM modulation. Towards the goal of achieving harmonic elimination and reactive power compensation with DSTATCOM, a 2.2-kV industrial three-phase, three-wire (3P3W) distribution system has been considered. For a 2.2-kV system, generally the inverter is equipped with a transformer for galvanic isolation and voltage matching between the industrial/utility distribution system voltage and the inverter voltage. However, weight and size of the transformer is more than 50% of the inverter. To alleviate this problem, the focus of this research is to design a SSBC based DSTATCOM without any line frequency transformer. The cascade number (N, i.e. the number of cascaded voltage source H-bridge inverters in each phase) is one of the most important design parameters for designing a transformerless PWM D-STATCOM. The value of N depends on the blocking voltage of the switching devices, cost, size and performance of the inverter. In the present work, IGBT has been used as the switching device and further, a cascade number of N equal to 2 has been chosen, considering percentage total harmonic distortion (%THD), the dc voltage requirement and the voltage rating of IGBT. This allows the use of 1.7-kV IGBTs, which are available readily at a reasonable cost. For this D-STATCOM, a suitable value of reference dc voltage for each H-bridge cell has been chosen. Ratings of various components of DSTATCOM such as DC capacitors for each H-bridge cell and inductance of coupling reactors have been designed and carefully selected. For a single phase D-STATCOM the pq theory is used for load harmonic current extraction but if supply voltage is distorted, then a proper Reference current generated for D-STATCOM is not possible. The modified single phase pq theory with PLL is used to generate a proper reference current for D-STATCOM. The performance of modified and original pq theory is compared for different harmonic and reactive power loads. The unequal power losses arising because of v asymmetries in device characteristics and the consequent deviation of capacitor voltages is investigated with an improved modulating signal method (IMS) and is compared to active voltage superposition (AVS) method. The performance of three-phase D-STATCOM largely depends on the control algorithm used for its implementation. The control algorithm considered in this work aims to eliminate harmonics, compensate reactive power as well as control and balance all the dc capacitor voltages of the SSBC in steady-state and in transient conditions. The load harmonic currents have been derived by using the measured voltages at point of common coupling (PCC), load currents, and the dc bus voltages of the H-bridge cells of the SSBC using Synchronous reference frame (SRP) theory. The performance of two current controllers namely PI and PI with resonant controller is investigated for different types of non-linear loads. In order to control the voltages of the floating dc capacitors of the 5-level SSBC based D-STATCOM while absorbing the unbalanced currents, the dc voltage balancing control has been divided into two control parts: (a) cluster voltage balancing control and (b) individual voltage balancing control. The former calculates the zero sequence voltage for balancing the three cluster voltages of the inverter and the later modifies the individual modulating signal for floating dc capacitors to follow their corresponding reference values. The capacitor voltage balancing method is investigated for unity power factor (UPF) and zero voltage regulation (ZVR) modes. Computer simulation studies under different load conditions have been carried out to verify the performance of the 3P3W D-STATCOM for harmonic elimination and reactive power compensation. The simulation study of the entire system has been carried out in MATLAB/Simulink environment. Extensive simulation studies have been carried out to investigate the performance of the D-STATCOM current controllers PI and PI with resonant. The simulation studies have been performed for both steady-state and transient conditions with different non-linear and reactive loads. Further, performance of the D-STATCOM has been investigated with unity power factor and zero voltage regulation mode, the capacitor voltage balancing among the individual dc capacitors of the D-STATCOM. In order to further verify the simulation studies of a single phase and a three-phase downscaled SSBC based inverter has been designed, constructed, and tested to verify the viability and effectiveness of the control theories, current controllers and capacitor voltage balancing methods. For hardware implementation, the power circuit of D-STATCOM is made with MOSFETs (IRFP460) as switching devices. Different hardware components as required for the operation of the experimental set-up such as pulse amplification, isolation circuit, dead-band vi circuit, voltage and current sensor circuits, and non-linear/reactive loads have been designed and developed. By using the Real-Time Workshop (RTW) of MATLAB and Real-Time Interface (RTI) feature of dSPACE-DS1006, the Simulink models of the various controllers of the prototypes have been implemented. The generated firing pulses have been given to the corresponding semiconductor devices of each H-bridge of the inverter through isolation, delay, and pulse amplification circuits in real-time. The developed prototype SSBC based D-STATCOM is used to verify the viability and effectiveness of the Current controllers for harmonic elimination and reactive compensation. In D-STATCOM implementation, each H-bridge cell is equipped with a galvanically isolated and floating dc capacitor without any power source or circuit. The SRF based controller of the DSTATCOM has been implemented in dSPACE. An uncontrolled rectifier with RL elements on DC side have been used as a nonlinear load. After compensation with D-STATCOM, the source currents have been observed to be sinusoidal and their corresponding THDs being within the limits of IEEE–519–1992 recommended value of 5%. The source displacement and power factors have been found to be close to unity. The switching response and the dynamic performance of D-STATCOM for a step change in the load have been studied and in both cases, a smooth control of source current has been achieved. The regulation of capacitor voltages has been ensured by the DC voltage regulator. A smooth control of dc voltages ensures the effectiveness of the DC voltage controller. Further, the experimental results of the capacitor voltage balancing dynamics of the H-bridge cells with zero sequence voltage injection and individual capacitor voltage balancing have been studied. The experimental results have been found to be in good agreement with the simulation results.