PROCESS INDUCED MECHANICAL STRESS AWARE CMOS CIRCUIT DESIGN

Abstract

At advance technology nodes layout dependent effects (LDEs) along with the supply voltage and temperature variations present serious challenges for circuit designers. Strain engineering and Inverse Narrow Width Effect (INWE) are the primary causes of LDEs, and supply voltage and temperature variations are due to circuits operating conditions. These effects can be termed as transistor level systematic variations. The variations result in reduced yield, increased cost of manufacturing and non-optimal circuit design, all being handled by keeping large design margins. Fortunately, the effect of these variations is systematic in nature, therefore, once modeled, these can be considered in circuit design methodologies (for optimizing transistors sizes and layout). Several analytical timing models have been presented to address this requirement. However, these models entail complex mathematical equations which limit their utility for a circuit designer or the models do not account LDEs. The models are having device/process level parameters, the accurate values of which are difficult to estimate. Moreover, the models can not be used at an early stage of a technology development. In this thesis, we present simple and accurate timing models, and systematic circuit design methodologies to optimize circuit performance in the presence of transistor level systematic variations, which can be effectively used by a designer at an early (prelayout) stage. In the first part of this thesis, we show that the average stress in a CMOS device channel varies significantly with the change in Number of Finger (NF) and Finger-Width (WF). Therefore, we model the channel stress as a function of NF and WF. We employ the stress model to express the effective current (Ie f f ) and logical effort (LE) of an Inverter/ NAND/NOR gates in terms of NF and WF. Subsequently, using these models, we develop a modified LE design methodology that can be used to optimize circuit performance in the presence of LDEs and INWE induced variations at initial pre-layout stage. We also propose an Ie f f model for a CMOS Inverter followed by a transmission gate (Inv-Tx) structure which is a part of many sequential circuits and widely used in multiplexers. We show that unlike Ie f f models of an inverter/NAND/NOR gates the Ie f f of an Inv-Tx cell is a function of both NMOS and PMOS for rising as well as falling transitions. We use the model to optimize Inv-Tx circuits considering transistor level systematic variations. We show that compared to the existing methodologies, circuits designed using our technique performs better in terms of speed and power dissipation. Further, we derive a setup time model for a static D-latch, which is used to simplify the setup time characterization considering transistor level systematic variations. The model is also useful to design the latch for a given setup time. Finally, we analyze existing Ie f f models for an inverter, NAND/NOR gates operating in the Near-Threshold-Voltage (NTV) regime and find that the models are not valid in the NTV regime. Subsequently, we present effective drive current models for an inverter and 2-input NAND/NOR gates in the NTV regime. Thereafter, employing Ie f f models, a modified near-threshold LE methodology is developed, which also considers transistor level i systematic variations at a pre-layout design stage which was missing in the earlier works. We show that the data-paths re-sized using the proposed methodology results in a significant performance improvement when compared to their conventionally designed counterparts. The results obtained in this thesis show that the effective current models are accurate enough to predict a cell performance in the presence of transistor level systematic variations. These models can either reduce the design time (when accurate SPICE models are available for a technology) or can be used to analyze circuits performance at an initial phase of technology development (when no SPICE models are available). Therefore, these models allow a designer to take decision regarding number of stages in a combinational cell, transistor sizes, layout level parameters at an early design phase. This will also reduce the number of design iterations.