DEVICE-CIRCUIT INTERACTIONS IN TUNNEL FET: AN ANALOG DESIGN PERSPECTIVE

Abstract

The static-power constrained applications have promoted the research on the steep slope transistor based analog/digital circuits. The prime objective is to overcome the problem of the MOSFET‘s ever-increasing leakage current while maintaining the performance. Therefore, the transistors with a steep subthreshold swing (SS) are being extensively investigated by the device research community. Among the emerging transistors, Tunnel FET (TFET) is one of the most promising by virtue of its ultra-low leakage current and MOSFET compatible fabrication processes. There are two kinds of TFETs, point and line TFET which are differentiated as per the direction of tunneling with respect to the gate. The steep slope of these devices makes them suitable for the sensing and other low power applications. However, the biasing schemes and the impact of device design parameters on the analog circuit performance have not been discussed in depth for TFETs. Bearing the above facts in mind, the biasing strategies and the small signal model for TFET need to be examined in detail. In addition, the drain current saturation voltage (VDSAT) and the body bias saturation voltage (VBSAT) are extremely important from the perspective of analog design. We investigated for the first time, a method to extract VDSAT for the point and line TFETs. The saturation in output characteristics of a point TFET is attained when the difference in the conduction band energy of the channel and drain is a few KBT. As the drain voltage (VDS) increases, the device initially enters in a soft saturation state and subsequently into deep saturation. The onset of soft and deep saturation happens for a constant difference in the gate-drain bias (VGD). We have also validated our results with the published experimental data. A soft saturation state in L-TFET is attained when the electron density in the epitaxial layer over the source saturates with the drain bias (VDS) and the conduction band energy gets pinned. In addition, at the onset of deep saturation, the electron density in the epitaxial layer over the channel drops below its doping level and the conduction band energy becomes invariant of any further increase in VDS. The transconductance and output resistance abruptly increases when the device enters in the soft saturation regime and attains a maximum in the deep saturation. The difference VGD is found to be a constant at the onset of saturation and remains independent of the gate-source overlap length (LOV). A shift in VDSAT and VGD is also observed with a change in ii the thickness and doping of the epitaxial layer. Further, a nominal change of ~ 5% in the voltage gain of a common source amplifier is observed when the n-device is either biased in soft or deep saturation regime, without any trade-off in the bandwidth. The proposed method is suitable for the analog design as VDSAT varies linearly with VGS. The impact of body bias (VBS) and gate-source overlap on the device-circuit analog performance of the epitaxial layer based L-TFETs is reported for the first time. The occupancy probability within the valence band of the source determines the modulation of ID with VBS. An increase of 40-60 % in ID with the reverse VBS is observed, while the forward VBS does not significantly alter the drain current. The reverse VBS at which ID attains the maximum value is defined as VBSAT, which changes almost linearly with VGS. We also proposed a mathematical model to determine VBSAT, bsed on the electrostastics of the gate-source overlap region. VBSAT increases with the gate-source overlap length (LOV) and decreases with the thickness of epitaxial layer. The intrinsic gain and unity gain cut-off frequency increase with the reverse VBS and remain nearly constant with the forward VBS. In general, the device width is being used to improve the drive capability in circuit design. We investigated that an increase in the gate-source overlap can also substantially enhance the analog performance of L-TFETs. Thus, we propose LOV variation-aware small signal model for L-TFETs based analog circuit design. This model can be used for appropriate sizing of the transistor for a target amplifier performance. The drain current initially increases linearly with LOV, and then exhibits a non-linear behavior. This is due to reduced effect of the lateral electric field at the far end of the gate-source overlap region. It is observed than an increase of 2.5× in LOV results in 2.33× increase in the voltage gain without any significant penalty in the bandwidth. Therefore, LOV can be used as an important design parameter in the analog circuit design, as it does not significantly change the output resistance and the gate-drain capacitance of the device.