Abstract:
In most of electronic application Memory is an essential part. To push the performance limit further, FinFETs are taken into consideration. It has confirmed to be promising alternative to take performance factor to next level because of their high resistance to SCE (short-channel effects). However, owing to its 3-D nature, high level of parasitics, which are significant in nm regime, degrade their high-speed analog and digital performances. In this dissertation we will get insight to reduce the impact and for that we have to find factors that affects parasitic components. In this dissertation, we are going to analytically derive an expression for the extraction of Outer fringe parasitic capacitance based on conformal mapping, which takes outer fringe field to be elliptical instead of circular, for better accuracy. Afterwards, using the same concept, i.e. elliptical inner fringe, field we will go for analytical derivation of Inner fringe parasitic capacitance. This model shows different geometrical parameter which affects parasitic capacitances. Lastly, comparison between modelled and simulation is done. Also, comparison between results of this work and other’s reported work result with different method is shown
