SYSTEMATIC VARIATION AWARE VCO DESIGN

Abstract

Scaling in CMOS technology has proved to be of great significance due to improved performance of design with low area and power requirement. But as we are moving towards lower technology nodes, many layout dependent effects come into picture which tends to impact performance of the design in unwanted manner. Thus it is becoming very important to avoid or reduce the impact of these effects on circuit performance parameters. It has become very necessary to predict these layout dependent effect in the earlier stages of circuit design cycle so that the overall number of iteration involved in circuit designing can be reduced. Many efforts has been done to tackle these problem by either compensating its impact or by modelling these effects. But all these efforts are still insufficient to make circuit systematic variation aware. Thus in this project work, optimisation of Voltage Controlled Oscillator (VCO) performance is done considering layout dependent effects like INWE, STI stress, etc. For the same, analysis of Current Starved VCO has been done and the impact of number of finger (nf) parameter of the MOSFET on device characteristics and thus on circuit performance parameters is analysed. Subsequently, a design methodology to optimize the nf in a multi-finger MOSFET to achieve optimum performance of the circuits has been proposed.