Abstract:
Supply voltage scaling is most effective method for reducing the energy consumption in digital circuits. Lot of work has been done in past to determine the fundamental limit of supply voltage for CMOS logic circuits. It has been shown that minimum supply voltage for MOSFET based ideal CMOS inverter is 36mV. Owing to their near ideal subthreshold characteristic FinFET device are more suitable for ultra-low voltage application hence an analysis has been done to find a similar fundamental limit for FinFETs. This fundamental limit is purely theoretical. The significance of such limit is in predicting a practical limit for circuit operation by considering variability and noise into consideration.
After establishing the minimum supply voltage for FinFET inverters, sizing issues for circuit operating near this fundamental limit have been discussed. Thus it has been shown that, if proper sizing is not done, the fundamental limit as established above is insufficient. For such cases we need to look at problem from circuit point of view. A problem for pass transistor followed by latch has been solved analytically using a modified expression for subthreshold current of FinFET device. Finally, temperature variability have been considered. For this purpose temperature dependence of subthreshold current equation has been established and validated. Minimum supply voltage limit is found to increase with temperature.
All simulation level work have been carried out using a table-based Verilog-A model data for which have been extracted using TCAD. In later part of report behavioral modelling for analog blocks of high speed serial IOs has been discussed.
