Abstract:
Due to rapid development in semiconductor industry, high package density in Integrated Circuits
is required. Scaling trend in CMOS technology dropped down to submicron levels. Also due to
small node capacitances, fewer amount of charge required for switching logical states, means
submicron devices are more prone to Single Event Effects (SEEs) due to radiations. This report
contain analysis of radiation induced SEEs in CMOS circuits, different radiation hardening
design techniques, proposed new radiation hardened design
Spice simulation environment created using Double exponential current pulse as glitch induced
due to radiations. Critical nodes are found out by applying radiation pulse on the CMOS circuits.
Effects of radiations are studied on the critical nodes, by varying peak current values, fall time
using Monte Carlo simulations.
Analysis of Radiation of Heavy Ion, Single Event Effect on 3D TCAD LATCH, to find out the
charge generated at different points along the length and angular radiation on the drain terminal
of the off device.
