Abstract:
This Dissertation describes the methodology followed in the implementation of Motion Pictures Expert Group (MPEG) standard for multimedia image processing using VHDL to be implemented over Field Programmable Gate Array (FPGA). As we know MPEG is a popular multimedia image compression standard used in various multimedia applications ranging from data storage to transmission of live video, thus, requiring high speed processing.
Presently, implementation of the standard is mostly done using high level languages, thus requiring central processing unit (CPU) to perform the task of brute force calculation on a continuous stream of data. This makes the speed of scheduled task on a multipurpose processor to slow down. This dissertation proposes a solution to this problem by transferring the task of implementing various algorithms under MPEG standard to be performed on a standalone hardware and thus, setting CPU free of any overhead.
FPGA being a flexible device from design point of view makes it possible to implement various modifications in the design as the up graded versions of standard comes in and thus, proves to be an economic alternative to presently popular CPLD device. This dissertation gives a detail flow of algorithms stated in ISO recommended MPEG standard implemented in hardware compatible very high speed integrated circuit hardware descriptor language. Here, an attempt has been made to remove three major type of redundancies namely Psycho Visual Redundancy, Inter Pixel Redundancy and Coding Redundancy.
