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OPTIMAL SEQUENCE OF SWITCHING COMPENSATORS FOR SYSTEM STABILITY IMPROVEMENT

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dc.contributor.author Jain, A. K.
dc.date.accessioned 2014-12-01T06:42:50Z
dc.date.available 2014-12-01T06:42:50Z
dc.date.issued 1981
dc.identifier M.Tech en_US
dc.identifier.uri http://hdl.handle.net/123456789/12454
dc.guide Bandyopadhyay, M. N.
dc.guide Mukhopadhyay, S.
dc.description.abstract Single Machine connected to infinite bus with two tie—lines is considered to study the effect of reactance on the system at different conditions. Different conditions here is meant by steady state, transient state (during fault) and Post fault. In steady state, it has been proved that the introduction of reactance (certain Value) enhances the stability region. For during fault and post fault study on Operating Point has been chosen and the fault has been made to occur at machine terminal itself i.e. very near to the bus in one of the lines. The most severe fault i.e. 3 Phase fault has been considered. It has been observed that during fault the system remains in step and after clearance of the fault if the system is left like that i.e. no introduction of reactance is made the system goes out for both the cases i.e. after fault if both the tie—lines are assumed to be commissioned or only one line is assumed to be commissioned. This condition can be avoided by switching suitable value of reactance at the time of clearance of the fault and it will reamin in the system till the oscillation is damped out. After that the system will be brought back to the original condition. That is to, say the suitable value of reactances are to be switched in and switched out at proper interval of time. en_US
dc.language.iso en en_US
dc.subject ELECTRICAL ENGINEERING en_US
dc.subject OPTIMAL SEQUENCE en_US
dc.subject SWITCHING COMPENSATORS en_US
dc.subject SYSTEM STABILITY IMPROVEMENT en_US
dc.title OPTIMAL SEQUENCE OF SWITCHING COMPENSATORS FOR SYSTEM STABILITY IMPROVEMENT en_US
dc.type M.Tech Dessertation en_US
dc.accession.number 177165 en_US


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