Abstract:
Interconnect play an important role in deep submicron technology. Rapidly decreasing minimum feature sizes lead to exponential growth of system-on-chip integration complexity. A novel circuit is introduced which eliminates the effects of interconnects on power dissipation, crosstalk, propagation delay and chip area by using bus encoding technique in RC modeled VLSI interconnect. Bus encoding techniques has been used to reduce inter-wire coupling which is primary source of power dissipation, crosstalk and delay in coupled interconnects. The proposed method focuses on simplified and improved circuit encoder for 4, 8 and 16 coupled lines. Previously used encoding schemes based on RC models had usually focused on only minimizing power dissipation and crosstalk while paying penalty in terms of chip area. However, our proposed encoder and decoder demonstrate an overall reduction in power dissipation by 68.7% through drastic reduction of switching activity. Furthermore, the propagation delay is reduced by 56.7% and other parameters like complexity, chip area and transistor count of the circuit is also minimized by more than 57%.
