Abstract:
Accurate estimation of delay in a circuit is a critical task in deep sub-micron technology due to process, voltage and temperature (PVT) variations. Look-Up-Table (LUT) based delay estimation method is the most widely used in Static Timing Analysis (STA). In this method, delay is obtained at some load capacitate Cl and input transistion time trip values using SPICE simulations and is estimated using linear interpolation at other values of C1 and t,.i,,. The timing parameters of a latch (setup time, hold time etc.) are expressed similarly in the LUT as a function of input transition, load capacitance and clock skew. One of the major challenges associated with the LUT based method is an appropriate choice of values of t,i,, Cl and clock skew which reduce the LUT generation time as well as increase accuracy of delay estimation. Our approach to solve this issue is that of identification of
regions of linear variation in delay or latch timing parameters with C1 and clock skew. We can then reduce the number of values of t,.i,,,, Ci and clock skew for which cell charcterization needs to be done. In this work, we identify the region of linear variation of setup time of a CMOS pass-transistor based latch with respect to trig and C1 in which we take appropriate care of its multistage nature and presence of feedback loop in it. We express the model coefficients and model's region of validity as a function of D-latch size. We use this model in reducing the CMOS latch's characterization time significantly while retaining accuracy in setup time estimation. We do not use device current/capacitive model in our work and hence this work is general enough to be -valid with scaling. With this work, . we were able to save approximately 66 % SPICE simulation during the standard cell library characterization. We have done simulations and validate our model using HSPICE. Delay predicted using our method is in good agreement with those of SPICE simulations with the said saving in simulation time.
