Abstract:
The nanowire (NW) gate-all-around (GAA) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) have potential to enable the Complementary MOS (CMOS)
downscaling beyond the roadmap that is, for deca-nanometer channel lengths. It has
minimum short channel effects and eliminated the requirement to scale gate dielectric thickness with channel length scaling thereby reducing the leakage currents in the device. The
nanowire devices, which are obtained by the top-down approach, are preferred over the bottom-up approach for being CMOS compatible and allowing precise control over the location of devices on substrate and circuit fabrication. Further, these devices have an added advantage of occupying least Silicon area on wafer because of its vertical pillar structure.
In order to reduce the costs and speed up the research and development of new devices and circuits, the Technology Computer Aided Design (TCAD) software packages are proving to be very useful. Hence these tools have been used to carry out an extensive scaling study on Vertical Silicon NW GAAFET 3D device structures.
The simulation results show that that these devices have best gate control over the channel
electrostatics owing to near ideal subthreshold-swing (SS) of 60mV/decade at room
temperature, Drain Induced Barrier Lowering (DIBL) < 50mV/V and a high Ion/Ioff ratio
(_106). In this work, a Two Wire Vertical CMOS Inverter (TWVI) obtained by combination
of matched n and p NW GAAFET is proposed and simulated. Along with TWVI, we also propose a Single Wire Vertical CMOS Inverter (SWVI) structure as an enhancement to TWVI. The device matching principle used for TWVI led to implementation of dual diameter
SVI. However, dual diameter SWVI approach shows severe impact of source pad and nanowire resistance. Thus, a single diameter SWVI is implemented to address source/drain resistance issue. The benchmarking of vertical CMOS with FinFET based inverter shows that the single diameter SWVI offers up to 80 % reduction in layout area and nearly 70 % reduction in power at the cost of 40% increase in delay.
The results show that these vertical devices have very high potential for use in ultra-low power applications and offers best overall performance for deca-nanoscale CMOS. As further extension of the work a transmission gate can be implemented by modifying the layout of SWVI structure. This will be of greater advantage as reconfigurable interconnects, where logic gates can be build in interconnects chain (pass transistor, inverter and transmission gate).
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