Abstract:
Process variations inducing transistor characteristics mismatch have emerged as major challenge to nano-scale circuit design leading to failure and yield loss of circuits such as sense amplifiers. In this work, these issues have been addressed and compensated sense amplifier circuits having high tolerance to process variations have been designed. The circuit designed with double gate FinFET technology, utilizes an improved self-compensation technique to overcome variations in transistor characteristics. It exploits the backgate of FinFET device for dynamic compensation against process variations.
The simulations of threshold voltage (Vi) mismatch using Monte-Carlo technique on CCLSA circuit show that the proposed circuit functions correctly even for worst case Vt mismatch of 50mV. The results are benchmarked with corresponding circuits reported in literature for area, speed and yield gain. This sense amplifier design shows excellent tolerance and offers up to 30% higher yield compared to uncompensated circuit reported in literature. The CCLSA design have minimal penalty for circuit complexity, speed, and is easily implementable at 45nm and 32nm technology nodes.
Further two more circuit styles namely IGSA (Independent Gate Sense Amplifier) and LBSA (Latch Based Sense Amplifier) using independent gate control in double gate FinFET have been designed. The dynamic compensation introduced earlier has been applied to these circuits. The compensated IGSA offers 25% higher yield and proves to be more insensitive to mismatch than uncompensated IGSA reported in literature. Also compensated LBSA circuit shows 15-20% more tolerance and can withstands 20inV more mismatch than LBSA circuit. This robustness is attributed to the compensation scheme designed. Performance comparisons of CCLSA, CIGSA, CLBSA show that CIGSA has the best over performance in terms of yield, power, delay and area.
This work can be extended by implementing these circuits in a device simulator where fine tuning of FinFET device parameters can be done. Layouts of the circuits can also be drawn and parasitic can be measured. Multi-fin structures which are not utilized in this work can be a possible option for reducing the delay.
