Nittala, Venkata SS Kumar

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dc.contributor.author	Nittala, Venkata SS Kumar
dc.date.accessioned	2014-11-30T06:30:39Z
dc.date.available	2014-11-30T06:30:39Z
dc.date.issued	2010
dc.identifier	M.Tech	en_US
dc.identifier.uri	http://hdl.handle.net/123456789/12226
dc.guide	Saxena, A. K.
dc.guide	Gupta, S. Das
dc.description.abstract	This thesis presents a new scheme of designing a low power 12-bit split capacitor array analog to digital converter (ADC). The proposed design involves a novel way so as to achieve low power and low area requirements. The design is targeted to cater the needs of micro sensor wireless applications. Low Power consumption is reported with moderate accuracy. In this thesis the design strategies for power effective medium/high resolution successive-approximation ADC are analyzed. The study considers reducing the power of the capacitive array with suitable capacitive attenuators that do not need non-unity capacitors. The design of minimum power comparators is analyzed and a novel comparator scheme, named time-domain comparator, is described. The input referred offset voltage of the time domain comparator reported is 70011v. The increase of resolution with reduced sampling is also analyzed and implemented. The different architectures of the Boot strapping were implemented to reduce the distortion of the sampling switch. The proposed methodologies, verified with a test design, are capable to provide 12-bit with 50-kHz signal band and 1-V supply. All the circuits in this work are implemented using Intel's 32 nm CMOS process	en_US
dc.language.iso	en	en_US
dc.subject	ELECTRONICS AND COMPUTER ENGINEERING	en_US
dc.subject	LOW POWER	en_US
dc.subject	SAR ADC DESIGN	en_US
dc.subject	DIGITAL CONVERTER	en_US
dc.title	"LOW POWER 12 BIT SAR ADC DESIGN"	en_US
dc.type	M.Tech Dessertation	en_US
dc.accession.number	G20239	en_US