Abstract:
The present dissertation work addresses a profound analysis on the development of the CMOS and BiCMOS logic circuits for a low voltage and low delay environment. The electronic industry has achieved a phenomenal growth over the last few decades, mainly due to the rapid advances in integration technologies and large scale system design. Typically, the required computational and information processing power of these applications is the driving force for the fast development of this field.
BiCMOS circuits are faster than that of the CMOS circuits due to higher current driving capability of the BJT. In the past ,due to a high degree of process complexity and the exorbitant costs involved, low power circuit design and applications involving CMOS and BiCMOS .technologies were used only in the applications where very low power dissipation was absolutely essential, such as wrist watches,pacemakers,and some integrated sensors. Although designers have different reasons for lowering power consumption and delay, depending upon the target application, minimizing the overall power consumption and delay in a system has become a high priority.
From the device designer's viewpoint, it has been said,"the lower the supply voltage, the better". Even though the dynamic power is largely dependent on the supply voltage, stray capacitances, and the frequency of the operation, the overall supply voltage has the largest effect. Therefore, with overall supply voltage lowered, the power dissipation can be reduced, without compromising the frequency of the operation. However, there are various problems associated with lowering the supply voltage. In the CMOS circuitry the driving capability of the MOSFETs decreases The supply voltage scaling in the BiCMOS circuits puts even more serious constraints on the circuit performance. There are various techniques to overcome this drawback which are discussed in this dissertation work.
