Abstract:
Since last few years in the way VLSI field, the capacity of on-chip memory is rapidly increasing to improve overall performance. According to the ITRS roadmap in 2001, memory will occupy about 90% of chip area by 2013. In such a memory-rich chip, the leakage current of a SRAM dominates the standby current. Thus, the leakage power consumption becomes a major issue. The aggressive scaling of Bulk CMOS has led to many SCE (short channel effects) such as • DIBL, Gate-tunneling current, GIDL, BTBT, Punch through. The subthreshold leakage has become a main issue and thus Bulk CMOS faces a roadblock and so it's the time to consider novel devices with lower SCEs. FinFET is one of the most promising device which is scalable even to sub-10nm. With lesser leakage currents' and near-ideal subthreshold slope it is most optimal for ultra-low power subthreshold operations.
This thesis first focus on Modeling of FinFET which includes capacitance modeling, drain current modeling and short-channel effects. The capacitance_ modeling is done analytically where as current modeling is done with help of simulators. The next parts focus on subthreshold operation which explores both optimal logic-style and device for subthreshold operation. In logic-style consideration we compare dynamic and static logic families. And in device consideration we compare Bulk MOSFET and FinFET. Finally we conclude with design of subthreshold SRAM with both Bulk MOSFET and FinFET, we have considered reliability issues such as Read stability and Hold stability for SRAM in final chapter.
