Abstract:
performance in Ultra Deep Submicron designs. Both start to play a crucial role with decreasing process nodes and increasing design density. In addition to this, crosstalk noise has an indirect dependence on process variations. A simple framework is proposed for doing statistical analysis of the effect of crosstalk noise on the functionality of logic gates. The dependence of functional noise on process variations is looked into by analyzing the variation of both glitch peak and area with process parameters. The effect of circuit and device parameters on delay noise and propagated noise is discussed. Thus the theoretical framework for statistical characterization of logic gates for noise rejection is laid down by proposing a statistical representation of the Noise Rejection Curves. The proposed framework is validated using parametric simulations in 90nm technology
