Abstract:
This thesis deals with the development of an emerging design approach in order to reduce significantly the power consumption of Systems on Chips (SoCs) and Communicating Objects. This work is focused on the development of an Analog to Digital Converter (ADC) which is a critical block in signal processing chains.
Most of the ADCs available till date are built on the synchronous or Nyquist sampling scheme. To achieve low power, in this .work, we attempt to develop an ADC driven only by the events contained in the useful signal. It means that an event is triggered only when the input signal crosses a particular amplitude level (level-crossing). This approach places the characteristics of these ADCs as the dual case of those of usual Nyquist converters: there is a sampling in amplitude and quantization in time. The advantages of such a sampling scheme can be fully exploited only when we choose an asynchronous design approach (no global clock) for its implementation. The ADCs of this class are known as Asynchronous Analog to Digital Converters (AADCs).
The focus of this thesis is to design and simulate a 16-Bit CMOS based Asynchronous Analog to Digital Converter (AADC) which uses both an irregular sampling in time of the analog signal (level crossing sampling) and an asynchronous design (no global clock). A Four stage micropipelining technique using Muller-C elements has been chosen to implement 4-phase handshaking protocol between successive stages.
The design can be broadly classified into analog and digital parts. Individual elements from each part are designed and simulation results are shown. The design is targeted to cater the needs of Bio-medical applications. It is developed on 90nm technology node with 1.2 Volts power supply. Simulations were performed in CADENCE Virtuoso Front to Back Design Environment. Maximum Power Consumption of less than 5mW and a conversion time of 6.5ns are reported.
