Abstract:
Images require substantial storage and transmission resources, thus image compression is advantageous to reduce these requirements.
Wavelet Transform has been successfully applied in different fields, ranging from pure mathematics to applied sciences. Pure software implementations of the Discrete Wavelet Transform, however, appear to be the performance bottleneck in real-time systems and suffer from power requirements. Therefore, hardware acceleration of the Discrete Wavelet Transform has become a topic of interest. We can reduce the logic and speed up our operations using Application Specific Integrated Circuits (ASICs). But main problem with ASICs are they require large time to market and initial investments are high. Before developing an ASIC we require to prototype our design. Field programmable Gate Arrays (FPGAs) prove to be a better solution for rapid prototyping. FPGAs are reprogrammable, have large number of logic cells suitable for implementing image Compression applications. We can explore the parallelism and pipelining feature of FPGA
The objective of this dissertation is design, simulation and synthesis of CDF biorthogonal Discrete Wavelet Transform on FPGA and developing a prototype of CDF biorthogonal Discrete Wavelet Transform processor. Initially, CDF Wavelet is studied and the hardware logic is designed. Then this hardware logic is realized and Simulated in Matlab Simulink using Xilinx System generator Blockset and synthesized on Spartan3E xc3s500e-4fg320 FPGA chip. Then using hardware co- - simulation feature of Spartan-3E starter kit, the results obtained in software and hardware simulations (i.e. on FPGA kit), are validated. The decomposed image of 512 x 512 at different levels from Matlab Silmulink using System generator shows good decomposition. Decomposed images has been reconstructed by using Matlab code and compared with the original images.
