Abstract:
Logic and memory circuit design in nanoscale regime requires control over leakage currents and process parameter variations. Metal Gate Double Gate (MGDG) MOSFET has been proved to be vital in nanoscale regime for its leakage reduction with appropriate second gate bias and reduced sensitivity to process parameter variations. Unfortunately leakage minimization techniques using body bias forces the design to have increased transition time. We demonstrated that SRAM cell designed with MGDG-MOSFET has the benefit of reduced transition time. We did analytical modeling of the small signal capacitances that affect circuit operation from which glitch voltage at the output has been evaluated and validated through HSPICE simulations and less glitch voltage has been observed for MGDG MOSFET compared to the bulk case. Also, we estimated all leakage currents by considering interconnect effect and used them in finding voltage rise/fall at the critical nodes of SRAM cell. We have emphasized on low leakage, high performance robust cache subarray design with the help of MGDG devices. Suppressing leakage currents and maintaining constant Static Noise Margin (SNM) in ultra low voltage operation is crucial for circuit designers. We did SNM analysis of SRAM designed using our gate work function Engineered MGDG MOSFET and it is confirmed through HSPICE simulations that the cell is able to maintain constant SNM at ultra low voltage operation and more robust to process variations.
