Abstract:
KEYWORDS: Universal Serial Bus Protocol (USB), OTG, UTMI, UTMI+, ULPI, VCS, SystemVerilog.
Freescale Semiconductors is working upon devising an integrated circuit for cellular subscriber device platforms, which aims at satisfying the requirements of high-tier products in the 2008-2009 time frame. Our focus is on one of its modules i.e., the USB 2.0 with OTG Support.
The USB2.0 protocol is a Serial protocol used at the interface for communication between the Host and the Device. It exploits differential data transmit advantage by just having 2 data lines. It is used to connect the external devices to the processor peripheral. The processor peripheral has IP bus interface to the other. Device peripheral will be USB compliant. There is OTG support which is capable of interchanging the roles of Host and Device. UTMI, UTMI+, ULPI interfaces which are introduced for the ease of modeling the USB protocol implementation for the IP vendors are also supported. All the simulations are compiled and run by using the tool VCS.
This project work aims at creation and simulation of a SystemVerilog based USB Verification IP for verifying the USB 2.0 OTG design. SystemVerilog provides a set of hardware. oriented modeling constructs within the context of C++ and Verilog and is emerging as a standard for high-level design, modeling & verification. The USB VIP supports USB2.0 functionality with OTG support for all the Interfaces Serial/UTM+/ULPI and all the speeds Low-/Full-/High-speed.
The Wireless USB is a Wireless protocol which is compatible with the existing USB2.0 which requires no wire connectors. The Physical Layer of the Wireless USB is implemented and verified in MATLAB which verifies all the modules present in the Physical Layer of the Wireless USB. The Program in MATLAB is done using ordinary OFDM instead of Multi Band OFDM as mentioned in the
