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| Issue Date | Title | Author(s) | Research Supervisor/ Guide | Type |
|---|---|---|---|---|
| 2013 | 3®DIMENSIONAL SIMULATION OF SINGLE EVENT UPSET OF 6T-SOI BASED 24 nm —FINFET -SRAM CELL | Jayaram, Namani | Dasgupta, Sudeb; Bulusu, Anand | M.Tech Dessertation |
| 2012 | MECHANICAL STRESS AWARE GATE TIMING MODEL FOR COMBINATIONAL LOGIC CELLS | Vundavalli, Sandeep | Bulusu, Anand; Dasgupta, Sudeb | M.Tech Dessertation |
| 2013 | T.CAD EVALUATION OF FIN ARCHITECTURE ON SOI SUBSTRATE AND ITS COMPARISON WITH PLANAR FDSOI 'MOSFET AT 28nm TECHNOLOGY NODE | Sahu, Prahlad Kumar | Sithanandam, R.; Bulusu, Anand; Dasgupta, Sudeb | M.Tech Dessertation |
| 2010 | ROBUST ANALOG VLSI CIRCUIT DESIGN | Kumar, Atul | Bulusu, Anand; Dasgupta, Sudeb | M.Tech Dessertation |