1. Shodhbhagirathi @ IITR

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Issue DateTitleAuthor(s)Research Supervisor/ Guide Type
1999. VLSI-CHIP FLOORPLAN AREA OPTIMIZATION BY GENETIC ALGORITHMGupta, Ravi KantSarkar, S.M.Tech Dessertation
1998TEMPERATURE SENSITIVITY OF SHANNON IMPLANTED SILICON MESFET THRESHOLD VOLTAGErao, D. L. NarasimhaSarkar, S.M.Tech Dessertation
2002LAY-OUT DESIGN OF ENCODER AND DECODER CHIP FOR MOBILE APPLICATIONSKumar, SatyendraJoshi, R. C.; Sarkar, S.M.Tech Dessertation
1997PERFORMANCE STUDY OF SERIES CONNECTED GUNN DIODES FOR MICROWAVE POWER GENERATIONSharma, Lieutenant SanjayAgarwal, R. P.; Sarkar, S.M.Tech Dessertation
1998AN ANALYTICAL STUDY OF SCHOTTKY BARRIER HEIGHT TAILORINGGhosh, JyotirmoySarkar, S.M.Tech Dessertation
1997COMPUTER SIMULATION OF GUNN DIODEReen, PinkuSarkar, S.M.Tech Dessertation
2003STUDY OF DYNAMIC CURRENT MODE LOGIC VLSI CIRCUITS"Singh, RajeerSarkar, S.M.Tech Dessertation
2003CHIP LEVEL DESIGN OF 4-BIT UNIVERS. SHIFT REGISTERVenugopal, N.Sarkar, S.M.Tech Dessertation
1996A STUDY OF IMPURITY DISTRIBUTION DEPENDENCE OF MESFET GATE-DRAIN BREAKDOWN VOLTAGEGarg, JitendraSarkar, S.M.Tech Dessertation
1996EFFECT OF DEVICE SCALING ON MESFET GATE BIAS VOLTAGE FOR DRAIN CURRENT ZERO TEMPERATURE COEFFICIENTSalgiya, SudhanshuSarkar, S.M.Tech Dessertation

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