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| Issue Date | Title | Author(s) | Research Supervisor/ Guide | Type |
|---|---|---|---|---|
| 2011 | A TIMING MODEL OF SEQUENTIAL CIRCUITS FOR EFFICIENT STANDARD CELL LIBRARY CHARACTERIZATION | Sharma, Yogendera | Bulusu, Anand; Saxena, Ashok Kumar | M.Tech Dessertation |
| 2011 | ANALYSIS OF UNDERLAP FINFET PARASITIC CAPACITANCE FOR CIRCUIT DESIGNING | Raycha, Swati | Bulusu, Anand; Saxena, A. K. | M.Tech Dessertation |
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