Please use this identifier to cite or link to this item: http://hdl.handle.net/123456789/9902
Title: COMPACT ANALYTICAL MODELING OF GATE LEAKAGE CURRENT WITH SOURCE/DRAIN OVERLAP FOR NANOSCALE N-MOSFET
Authors: Kumar, Ashwani
Keywords: ELECTRONICS AND COMPUTER ENGINEERING
GATE LEAKAGE CURRENT
SOURCE/DRAIN OVERLAP
NANOSCALE N-MOSFET
Issue Date: 2006
Abstract: Aggressive scaling of the gate oxide thickness has made gate tunneling current an essential aspect of the metal-oxide-semiconductor field-effect transistor (MOSFET) modeling. Consequently, the modeling of the different component of gate tunneling current is very important for the estimation of gate leakage power, especially for low power application. In this work, an analytical scheme for channel and source/drain overlap region gate tunneling current through ultra thin gate oxide of n-channel MOSFET including quantization effect, and non-uniform dopant profile in vertical direction in poly-gate and fringing field effect in the gate sidewall has been developed for sub50-nm generation MOSFET device. The results obtained are the basis of our analytical model, are in close match with the reported experimental results, thus validating the modeling scheme developed. The non-uniform dopant profile in poly-gate and fringing field effect in the gate sidewall has been included in the analytical scheme for the first time. The simplicity of the proposed model is suitable enough to use it for circuit simulator. The proposed model is capable of predicting the gate tunneling current under positive as well as negative gate bias. It is observed that neglecting the non-uniform dopant distribution in vertical direction in poly gate and fringing field effect in the gate sidewall may lead to large error in the calculated gate tunneling current. The results provide a guideline to the severity of this effect from the point of view of standby power consumption. It is also shown that gate-tunneling current is almost insensitive to temperature and substrate bias variation. The gate tunneling current variation with gate bias, gate oxide thickness and source/drain overlap region have also been assessed.
URI: http://hdl.handle.net/123456789/9902
Other Identifiers: M.Tech
Appears in Collections:MASTERS' DISSERTATIONS (E & C)

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