Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/9892
Title: TRANSACTION LEVEL MODELING AND SYNTHESIS USING SYSTEMC
Authors: Sudheer, Y. S. V.
Keywords: ELECTRONICS AND COMPUTER ENGINEERING;TRANSACTION LEVEL MODELING AND SYNTHESIS;SYSTEMC;SYSTEM-ON-CHIP
Issue Date: 2006
Abstract: In order to handle the ever increasing complexity of System-on-Chips (SoCs) and time-to-market pressures, the design abstraction has been raised to the system level. This higher level of abstraction generated large interest in Transaction Level Modeling (TLM), synthesis and verification. In TLM, the details of communication among computation components are. separated from the details of computation components. A model developed at higher level of abstraction allows one to handle complexity by initially hiding the details and elaborating them later. A higher level of abstraction makes less simulation time, ease of development of model of the system and less prone to errors in later phases of the design cycle. In this thesis we have modeled CDMA IS-95 Forward link traffic channels and GSM encoder and decoder blocks using SystemC. SystemC is an emerging modeling platform that supports design abstraction at various Ievels of modeling like, Register Transfer Level (RTL), behavioral, and system level. We have compared execution times of CDMA and GSM blocks with gate level SystemC model that is obtained from SystemCrafter, a tool for synthesizing SystemC code. The accuracy of TLM is same as gate level model, moreover TLM has more flexibility, less time to develop and easy to verify
URI: http://hdl.handle.net/123456789/9892
Other Identifiers: M.Tech
Research Supervisor/ Guide: Joshi, R. C.
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' DISSERTATIONS (E & C)

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