ARCHITECTURE DESIGN AND FPGA IMPLEMENTATION OF AN IMAGE ENHANCEMENT SYSTEM

Abstract

The field of digital image processing is continually evolving. During the last decade, there has been a significant increase in the level of image contrast and intensity enhancement through various algorithms of digital image processing. With the help of VLSI CAD tools the designer is enable to simulate the behavior of incredibly complex algorithms and thus determine whether the obtained design meets the desired specifications. If the errors are found, appropriate changes are made and verification of new design is repeated through simulation. In this thesis the design of histogram equalization algorithm from architecture level to chip level layout is presented. Design constraints are obtained from the software Xilinx 1SE (integrated software Environment) 5.2i version. VHDL code of the algorithm is prepared based on the structural-Behavioral description of the model. Functional verification of the design has been implemented using Modelsim simulator (version 5.6).Finally the algorithm is implemented in Spartan FPGA devices