Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/9817
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dc.contributor.authorSingh, Rajeer-
dc.date.accessioned2014-11-20T10:56:09Z-
dc.date.available2014-11-20T10:56:09Z-
dc.date.issued2003-
dc.identifierM.Techen_US
dc.identifier.urihttp://hdl.handle.net/123456789/9817-
dc.guideSarkar, S.-
dc.description.abstractThis dissertation introduces a new reduced swing logic style called Dynamic Current Mode Logic (DyCML) that reduces both gate and interconnect power dissipation. DyCML circuits combine the advantages of MOS Current Mode Logic (MCML) circuits with those of dynamic logic families to achieve high performance at a low-supply voltage with low-power dissipation. Unlike Current Mode Logic (CML) circuits, DyCML gates do not have a static current source, which makes DyCML a good candidate for portable devices and battery-powered systems. Simulation and test results show that DyCML circuits are superior to other logic styles in terms of power and delay. The Cell Library is designed by using DyCML Logic in 211 CMOS technology. The results of CMOS Technology circuits and DyCML circuits show the differences in these two.en_US
dc.language.isoenen_US
dc.subjectELECTRONICS AND COMPUTER ENGINEERINGen_US
dc.subjectDYNAMIC CURRENT MODE LOGIC VLSI CIRCUITSen_US
dc.subjectMOS CURRENT MODE LOGICen_US
dc.subjectCMOS TECHNOLOGYen_US
dc.titleSTUDY OF DYNAMIC CURRENT MODE LOGIC VLSI CIRCUITS"en_US
dc.typeM.Tech Dessertationen_US
dc.accession.numberG11441en_US
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