PERFORMANCE CHARACTERISTICS OF VLSI INTERCONNECT LAYOUT

Abstract

For deep submicron (DSM) very large scale integration (VLSI) designs, interconnect has become a dominant factor in determining the overall circuit performance. Interconnect layout plays a vital role in the performance characteristics of interconnects and thus on the overall chip performance. For this efficient layout (routing) of interconnect is to be done so as to optimize the interconnect performance. Also in today deep submicron VLSI circuits interconnect delay dominates the gate. delay. Currently, inductance is becoming more important with faster on-chip rise times and longer wire lengths. With these trends, it is becoming more important to include inductance when modeling on-chip interconnect for better performance of interconnect. To achieve the above, this dissertation presents a stochastic interconnect (wiring) distribution model under certain assumptions, so as to get a priori knowledge about the performance of interconnect before the final circuit is laid out. The interconnect performance characteristics are then obtained. Routing of interconnect is done on the benchmark circuit, "Motorola 8-bit Bidirectional Universal Shift Register" to calculate the length of interconnect and the performance characteristics of interconnect such as area, power and delay due to interconnect. For the calculation of performance characteristics of interconnect, distributed RLC model of interconnect is taken. The two results prior to the layout of interconnect and after routing are compared with that of the benchmark circuit. In the end a methodology for optimal repeater insertion is proposed to further reduce the delay due to interconnect as expected from today's high speed circuitry. The work is done in MATLAB and Turbo C++ on Windows 9x environment.