DESIGN OF SIGNAL STATUS MONITORING CHIP

Abstract

This thesis work presents a complete design of Signal Status Monitoring System (SSM system) from its logical block diagram to chip level layout. This system displays the signal status of some electronic switches that has been transmitted from a remote transmitter. This thesis work also focuses the design scheme based on the CAD (Tanner) tools. First, a complete architectural design of each block up to the gate level has been developed. Then design is captured in behavioral and structural VHDL coding using Xilinx Foundation Series 2.1. It has been synthesized and simulated to check its functionality using the same software. Timing analysis of synthesized circuit is done to get the timing specifications. Main focus is given to the calculation part in which an attempt has been made to meet the timing specifications with minimum chip area. Aspect ratio of each transistor is calculated using the model parameters of 2μm technology of Tanner tools. From these calculated values layout of the design is drawn using L-Edit of Tanner tool. This layout design is finally extracted to T-SPICE for simulation. A comparison is made between timing reports generated by the two softwares,