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dc.contributor.authorNiranjan, Vandana-
dc.date.accessioned2014-11-20T08:33:13Z-
dc.date.available2014-11-20T08:33:13Z-
dc.date.issued2002-
dc.identifierM.Techen_US
dc.identifier.urihttp://hdl.handle.net/123456789/9752-
dc.guideAggarwal, R. P.-
dc.description.abstractThis work deals with design and gate-level implementation of Universal Asynchronous Receiver Transmitter (UART) Chip. The UART chip takes the parallel information from the computer and translates it into serial data for the link. At the receiving end a UART will convert the serial data stream back into parallel data so that the peripheral or other computer can understand. This work focuses design methodology based on tools and techniques to capture the design, to simulate it at several levels of abstraction, and to implement it through synthesis, thus makes it easy to develop a hardware prototype. Once we evaluate the prototype, it is relatively easy to change the design at the VHDL level and thenresynthesize it to ensure that the design meets the required specifications. Thus the design includes behavioral model development, test bench generation, simulation, and logic synthesis using synopsys tool suite. To start with first behavioral VHDL code i.e. description which specifies what the system is expected to do, without reference to its actual internal structure, in the form of an executable program, was written based on the block diagram of the chip. Then this code was analyzed to remove all the possible errors in the code using VHDL Analyzer. VHDL System Simulator (VSS) then simulated the debugged VHDL code to check the functionality of the chip as per the specifications. Next was to synthesize the chip using Design Compiler of Synopsys logic synthesis tool which automatically converts VHDL description to a gate-level implementation in a given technology. I have implemented my chip in Isi_10k technology. Synopsys logic optimization tool then transformed the synthesized UART Chip to a smaller and faster circuit and the information gained from the synthesized and optimized circuits was applied back to the VHDL description, to fine-tune architectural decisions. After synthesis, chip was again simulated and comparison of post and pre synthesis simulation results concluded that chip was designed as per the specifications known as verification process. Lastly design check was applied to the implemented chip, which generated an output report showing all the parameters about the designed chip.en_US
dc.language.isoenen_US
dc.subjectELECTRONICS AND COMPUTER ENGINEERINGen_US
dc.subjectUART CHIP DESIGNen_US
dc.subjectVHDLen_US
dc.subjectVHDL SYSTEM SIMULATORen_US
dc.titleUART CHIP DESIGN USING VHDLen_US
dc.typeM.Tech Dessertationen_US
dc.accession.numberG10726en_US
Appears in Collections:MASTERS' DISSERTATIONS (E & C)

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