IMPROVED SINGLE TRANSISTOR EQUIVALENT FOR CMOS INVERTER

Abstract

The development of an equivalent single transistor model of a CMOS inverter is considered . It is shown that the channel lengths of the equivalent single transistors - for both high-to-low and low-to-high transitions are not equal to those of original transistors . An average of the equivalent transistor lengths obtained from 50% and 90% delays, yield minimum error in output voltage evaluation .. The analytical procedure also takes into account various possible conduction states (linear , saturation and cut-off) of the original transistors during the input transition periods .