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DC Field | Value | Language |
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dc.contributor.author | Joshi, Sanjay | - |
dc.date.accessioned | 2014-11-20T08:12:59Z | - |
dc.date.available | 2014-11-20T08:12:59Z | - |
dc.date.issued | 2001 | - |
dc.identifier | M.Tech | en_US |
dc.identifier.uri | http://hdl.handle.net/123456789/9737 | - |
dc.guide | Aggarwal, R. P. | - |
dc.description.abstract | INTRODUCTION: Over the past several years Silicon CMOS technology has become the dominant fabrication process for high performance and cost effective VLSI circuits. The revolutionary nature of the development is the capability of integrated number of .. transistors in the circuit on a single chip has grown. In order to improve on this throughput rate it will be necessary to improve the technology both in terms of scaling and processing. VLSI technology provide the user with new and more complex range of off the shelf circuits and processes that can readily be used in the design of special circuits of considerable complexity. This provides with a new degree of freedom to the designers. With the rapid evolution of the design technology time-to-market is one of the crucial factors in the ultimate success of a component. Designers are increasingly adhered to the rigid design methodologies and strategies which are more amenable to design automation. Instead of the individualized approach of the earlier design, a circuit is designed using hierarchical approach or a earlier design for e.g. any circuit is a collection of modules each of which consists of a number of cells on it's own. Cells are reused as much as possible to reduce the design effort and to enhance the chances for a first-time-right implementation. The fact that this hierarchical approach is at all possible is the key ingredient for the success of digital circuit design. The abstraction levels in digital circuit design are in order of increasing abstraction the device, the circuit, the gate and the functional module | en_US |
dc.language.iso | en | en_US |
dc.subject | ELECTRONICS AND COMPUTER ENGINEERING | en_US |
dc.subject | ADDER CHIPS | en_US |
dc.subject | CMOS TECHNOLOGY | en_US |
dc.subject | VLSI TECHNOLOGY | en_US |
dc.title | DESIGN AND PERFORMANCE CHARACTERISTICS OF ADDER CHIPS | en_US |
dc.type | M.Tech Dessertation | en_US |
dc.accession.number | G10573 | en_US |
Appears in Collections: | MASTERS' THESES (E & C) |
Files in This Item:
File | Description | Size | Format | |
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ECDG10573.pdf | 3.1 MB | Adobe PDF | View/Open |
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