EXCLUSIVE-OR GATE LAYOUT DESIGN AND PERFORMANCE SIMULATION

Abstract

Layout of an Exclusive-OR( XOR) gate as well as the schematic of an XOR gate for different channel widths are drawn using LASI (Layout System for Individuals). LASI is a powerful CAD package used in the design of integrated circuits. It has utility programs such as the Spile file compiler circuit LASICKT which also works with the schematics. In the First stage the schematic of an XOR gate is drawn with the channel dimensions of Wn=3u, Wp=9u and Ln=Lp=2u. Spice circuit file is generated for the XOR schematic by running the LASICKT Spice file compiler. The schematic performance is then verified by simulating this Spice circuit file using Aim-Spice. And then Layout is drawn for the XOR gate with the above channel dimensions. After drawing the Layout, design rule checking is done using LASI design rule check utility LASIDRC. In the next step, LVS (Layout Vs Schematic) comparison is done using LASICKT for verifying the node connections between schematic and layout. Running the LASICKT will gives the Spice circuit file for the drawn XOR Layout. The circuit file is then simulated using Aim-spice with different input combinations to verify the truth table of XOR gate. In the second stage Layout of XOR gate is drawn for the channel dimensions of Wn=10u, Wp=30u and Ln=Lp=2u. Because of the Large channel width compared to the previous Layout, parallel combination of the MOSFETs is taken for getting the desired channel width and then the procedure of stage 1 followed for drawing and performance verification of the XOR gate Layout.