CHIP LEVEL DESIGN OF 4-BIT UNIVERS. SHIFT REGISTER

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DC Field	Value	Language
dc.contributor.author	Venugopal, N.	-
dc.date.accessioned	2014-11-20T04:25:19Z	-
dc.date.available	2014-11-20T04:25:19Z	-
dc.date.issued	2003	-
dc.identifier	M.Tech	en_US
dc.identifier.uri	http://hdl.handle.net/123456789/9651	-
dc.guide	Sarkar, S.	-
dc.description.abstract	As Digital Systems have become more and more complex, detailed design of the system at the gate and flip-flop level has become very tedious and time consuming. For this reason, use of Hardware description languages in the Digital Design process continues to grow in importance. An HDL (Hardware Description Language) allows a Digital system to be designed and debugged at a higher level before conversion to Gate and Flip-Flop level.	en_US
dc.language.iso	en	en_US
dc.subject	ELECTRONICS AND COMPUTER ENGINEERING	en_US
dc.subject	CHIP LEVEL DESIGN	en_US
dc.subject	DIGITAL SYSTEMS	en_US
dc.subject	FLIP-FLOP LEVEL	en_US
dc.title	CHIP LEVEL DESIGN OF 4-BIT UNIVERS. SHIFT REGISTER	en_US
dc.type	M.Tech Dessertation	en_US
dc.accession.number	G11132	en_US
Appears in Collections:	MASTERS' THESES (E & C)

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