IMPLEMENTATION OF LINEAR PREDICTIVE CODING SPEECH FILTER

Abstract

This dissertation describes the complete process of simulation, synthesis and implementation of LINEAR PREDICTIVE CODING SPEECH FILTER used in transmitter / receiver for source coding. Linear Predictive Coding (LPC) is one of the most important speech coding techniques. Speech prediction/synthesis filter is the most important section of transmitter / receiver in any source coding methods for example Voice Excited Linear Predictive coding (YELP), Code Excited Linear Predictive coding (CELP), Regular Pulse Excited Linear Predictive Coding (RPE-LPC), etc. Development of architecture for filter implementation in lattice structure with one Multiplier And Accumulator (MAC) is stressed here. This architecture is coded in VHDL language. N1odelSim, Synopsys FPGA compiler-Il, Xilinx Alliance Series are the different software tolls used in implementing the design. ModelSim is used for pre and post simulation. Simulation results give the verification of design functionality. Synopsys FPGA Compiler II is used for synthesis. Synthesis is the first stage in backend design where constraint orientation starts. Xilinx Alliance Series is used for place and route and generating bit file for Xilinx FPGA chip xc4020xla-07-pgl60. In this dissertation work 16-bit internal operation is performed but one can design up-to 36-bits precision