LAY-OUT DESIGN OF ENCODER AND DECODER CHIP FOR MOBILE APPLICATIONS

Abstract

In convolutional codes, the encoding operation may be viewed as the discrete-time convolution of the input sequence with the impulse response (or generator polynomial) of the encoder. The convolutional encoder employs a sequential model for encoding the data. Every transmission of data is characterized by a change in state (called the FINITE STATE MODEL) of the system. Therefore, tracking the state of the system is equivalent to tracking the data that is sent. This is the principle of the convolutional encoder/decoder. The Viterbi decoder accepts the noisy encoded bit sequence and attempts to recover the information content of the original encoded message. This is done by iteratively computing the Hamming (hard-decision decoding) distances between the received code word and the possible transmitted 2k code words then the code word that was closest in distance to the received code word is selected. In this dissertation the designs of Convolutional encoder and Viterbi decoder are described in Verilog-HDL, then simulated and verified with a noise adder on ModelSim and . VCS and then synthesized on Synopsys tool. Finally the Layout of the Convolutional encoder and Viterbi decoder chips are generated using Tanner Tools. L-Edit was used for this purpose and the L-Edit/SPR TM module of this tool was utilized. 3 IIT