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http://localhost:8081/xmlui/handle/123456789/9619Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Agarwal, Deepak | - |
| dc.date.accessioned | 2014-11-19T14:07:16Z | - |
| dc.date.available | 2014-11-19T14:07:16Z | - |
| dc.date.issued | 1999 | - |
| dc.identifier | M.Tech | en_US |
| dc.identifier.uri | http://hdl.handle.net/123456789/9619 | - |
| dc.guide | Agarwal, R. P. | - |
| dc.description.abstract | A CAD tool has been developed on Tata ELAXSI 3200 dual processor under UNIX environment in C-programming language for test pattern generation for digital circuits. Which is used to diagnose the nature of the fault (stuck-at-1 or stuck-at-0) at any signal line or at gate output in the digital circuit. Results of the developed software have been validated experimentally using a typical digital circuit.. | en_US |
| dc.language.iso | en | en_US |
| dc.subject | ELECTRONICS AND COMPUTER ENGINEERING | en_US |
| dc.subject | CAD TOOL | en_US |
| dc.subject | TEST PATTERN GENERATION | en_US |
| dc.subject | DIGITAL CIRCUITS | en_US |
| dc.title | A CAD TOOL FOR TEST PATTERN GENERATION FOR DIGITAL CIRCUITS | en_US |
| dc.type | M.Tech Dessertation | en_US |
| dc.accession.number | 248301 | en_US |
| Appears in Collections: | MASTERS' THESES (E & C) | |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| ECD248301.pdf | 3.42 MB | Adobe PDF | View/Open |
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