Please use this identifier to cite or link to this item:
http://localhost:8081/xmlui/handle/123456789/9619| Title: | A CAD TOOL FOR TEST PATTERN GENERATION FOR DIGITAL CIRCUITS |
| Authors: | Agarwal, Deepak |
| Keywords: | ELECTRONICS AND COMPUTER ENGINEERING;CAD TOOL;TEST PATTERN GENERATION;DIGITAL CIRCUITS |
| Issue Date: | 1999 |
| Abstract: | A CAD tool has been developed on Tata ELAXSI 3200 dual processor under UNIX environment in C-programming language for test pattern generation for digital circuits. Which is used to diagnose the nature of the fault (stuck-at-1 or stuck-at-0) at any signal line or at gate output in the digital circuit. Results of the developed software have been validated experimentally using a typical digital circuit.. |
| URI: | http://hdl.handle.net/123456789/9619 |
| Other Identifiers: | M.Tech |
| Research Supervisor/ Guide: | Agarwal, R. P. |
| metadata.dc.type: | M.Tech Dessertation |
| Appears in Collections: | MASTERS' THESES (E & C) |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| ECD248301.pdf | 3.42 MB | Adobe PDF | View/Open |
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