Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/9585
Title: . VLSI-CHIP FLOORPLAN AREA OPTIMIZATION BY GENETIC ALGORITHM
Authors: Gupta, Ravi Kant
Keywords: ELECTRONICS AND COMPUTER ENGINEERING;VLSI-CHIP FLOOR PLAN AREA;GENETIC ALGORITHM;SELF ADAPTING MESSY GENETIC ALGORITHM
Issue Date: 1999
Abstract: This dissertation describes a Self Adapting Messy Genetic Algorithm for Floorplan Area Optimization problem. The algorithm is based on suitable techniques for individual arrangement in population, their selection, solution encoding and evaluation function definition, effective modified heuristic operators, crossover,. mutation & RB-90 operators which further improve the method's effectiveness. Experimental results show that the modified algorithm is better than the existing algorithm as far as the CPU time requirements and result accuracy is considered. It requires a limited amount of memory, it is not sensible to special structures as it is independent from floorplan topology. Finally it is demonstrated that the modified algorithm is well suited for floorplan problems in which total number of implementations are large.
URI: http://hdl.handle.net/123456789/9585
Other Identifiers: M.Tech
Research Supervisor/ Guide: Sarkar, S.
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' DISSERTATIONS (E & C)

Files in This Item:
File Description SizeFormat 
ECD247968.pdf6.71 MBAdobe PDFView/Open


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.